Three-dimensional memory design progress [Full text]

In recent days, the Phase Change Memory Research Group of the Shanghai Institute of Microsystems and Information Technology of the Chinese Academy of Sciences has made progress in the field of 3D memory design. The research results were published on the A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM. On IEEE Transactions on Circuits and Systems II: Express Briefs.

Phase change memory uses electric pulses to induce the memory material to switch between amorphous and crystalline states. It has the advantages of non-volatile, long cycle life, fast writing speed, good stability, and low power consumption. It is considered by the industry as the next generation. One of the best solutions for storage technology.

Three-dimensional integration technology stacks chips or devices in the vertical direction, which can significantly increase chip integration. It is an important technology that continues Moore's Law. Among them, a cross-point three-dimensional storage structure is widely used in non-volatile memory.

At present, the research of three-dimensional new non-volatile memory focuses on the device and array level. Different from the traditional two-dimensional memory, the three-dimensional phase change memory uses a novel Ovonic Threshold Switch (OTS) device as a selector. According to the physical characteristics of the OTS device and the characteristics of the three-dimensional cross-stacked array structure, the three-dimensional cross-stacked phase change memory employs a V/2 bias method to implement the operation of the memory cell, but the V/2 bias method and the OTS device lead to the array. In many non-selected memory cell leakage, leakage results in readout circuit read rate and read speed degradation. As memory reads, parasitic devices in the array reduce read speeds. In the two-dimensional memory, these devices are mainly concentrated in the plane direction; however, in the three-dimensional memory, the parasitic devices in the vertical direction further reduce the reading speed. Therefore, it is necessary to quantify the factors affecting the read operation of the three-dimensional memory and to increase the speed of the integrated circuit design.

The researchers designed the array core circuit of the three-dimensional phase change memory, analyzed the read path of the three-dimensional phase change memory, and summarized the five factors that affect the read operation of the three-dimensional phase change memory. The quantitative relationship between these five factors and the three-dimensional memory array parameters is also pointed out. Based on this, the paper proposes a single reference and parasitic matching readout circuit suitable for three-dimensional memory. The circuit uses a changing reference current and matches the above five factors in the read direction and the reference direction. Experimental results show that the readout time is 79% shorter than the traditional method, and the number of misreads is reduced by 97%. The readout circuit presented in this paper can be applied to other three-dimensional cross-stacked non-volatile memories, and is directly related to the design parameters of the readout circuit and the array. According to the memory capacity of the related designer, the design can be applied to different memory capacities. High-performance readout circuit. In this paper, for the first time in the world, the five factors that affect the read operation of the three-dimensional cross-stack memory are summarized, and the first read circuit related to the characteristics of the new three-dimensional non-volatile memory array is proposed. This is the first article in the world. Three-dimensional phase change memory read design article.

The research work was supported by the Chinese Academy of Sciences’ strategic pilot technology project, the national integrated circuit major project, the National Natural Science Foundation, and the Shanghai Science and Technology Commission.

(Source: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences)